Integrated circuit having a level of metallization of variable thickness

ABSTRACT

An integrated circuit comprising at least one level of metallization, the level of metallization being provided with tracks and comprising metal portions having at least two different thicknesses. The level of metallization comprises at the same time at least one inductor and at least one track, the track being formed on a portion of small thickness, and the inductor being formed on a portion of large thickness.

BACKGROUND OF THE INVENTION

The invention relates to an integrated circuit comprising at least onelevel of metallization, the level of metallization being provided withtracks and comprising metal portions of at least two differentthicknesses.

A level of metallization usually comprises metal tracks of smallthickness, for example 1 micron, and small width, for example 1 micron.These metal tracks are used to transfer logic data. To manufactureinductors with an inductance of several nanohenrys, a separate level ofmetallization may be provided which is employed only for this purpose.In order to reduce the resistance of these inductors, particularly thedirect-current resistance, use is made of inductors having a large widthof, for example, 20 μm, and a large thickness of, for example, 2.5 μm.

However, it is rather unsatisfactory to use a level of metallizationonly for inductors as a large area of this level of metallizationremains unused. For this reason it would be desirable to take measuresenabling said level of metallization to also comprise tracks for thetransfer of logic data, said tracks having a small width. However, it isvery difficult to manufacture tracks which are narrow and thick.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an integratedcircuit having a level of metallization comprising both an inductor anda track for, for example, transfer of logic data.

To achieve this, the integrated circuit in accordance with the inventionis characterized in that the level of metallization comprises at thesame time at least one inductor and at least one track, the track beingformed on a portion of small thickness, and the inductor being formed ona portion of large thickness.

The coupling between the turns of wire of the inductor is only slightlyaffected by the profiles of the portions having a large thickness, whichinclude a first part at the bottom of the step having a straight edgeand a second concave part.

In an embodiment of the invention, the level of metallization comprisesa first metal layer and a second metal layer, which are separated by astop layer. The second metal layer may have a larger thickness than thefirst metal layer.

A further object of the invention is to provide a method ofmanufacturing a level of metallization of an integrated circuit, thelevel of metallization being provided with tracks. A first metal layeris provided, whereafter a stop layer and a second metal layer areapplied. A first mask of a resin is provided on the circuit. The secondmetal layer is subjected to photoetching down to the stop layer. Asecond resin mask is deposited on the circuit. The stop layer and thefirst metal layer are etched, in such a manner that portions comprisingthe first metal layer and the second metal layer and portions comprisingonly the first metal layer remain intact.

After photoetching the second metal layer, the first mask may be removedor preserved.

In this manner, an integrated circuit is obtained wherein the use of alevel of metallization is optimized, which enables the number of levelsof metallization to be reduced, resulting in a smaller thickness of theintegrated circuit and in a saving in costs owing to the smaller numberof process steps, or, the performance of the integrated circuit to beincreased if the number of levels of metallization remains unchanged.

These and other aspects of the invention will be apparent from andelucidated, by way of non-limitative example, with reference to theembodiment(s) described hereinafter.

BRIEF DESCRIPTION OF THE DRAWING

In the drawings:

FIGS. 1 a through 1 f are diagrammatic, cross-sectional views of amethod in accordance with the invention; and

FIGS. 2 a through 2 f show a modification of the preceding Figures.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

As shown in FIG. 1 a, a first metal layer 2 is deposited, in a thicknessof approximately 1 μm, on the upper dielectric layer 1 of an integratedcircuit. Subsequently, a stop layer 3 having a small thickness of, forexample, 300 Å is deposited on the first metal layer 2. This stop layer3 may be made from titanium or titanium nitride. Next, a second metallayer 4, having a thickness of for example 2 μm, is deposited.

In the step shown in FIG. 1 b, a first resin mask 5 is provided on thesecond metal layer 4. The areas protected by the mask 5 are defined bymeans of a photorepeater.

FIG. 1 c shows that the second metal layer 4 is subjected to an etchingprocess, i.e. an isotropic wet etching process. By means of said wetetching process the second metal layer 4 can be removed, with theexception of the regions protected by the mask 5. However, the regions 6of the second metal layer 4 adjoining the lateral edges 5 a of the mask5 are subject to erosion during said wet etching process. This erosionresults in a concave lateral edge of the second metal layer 4. Etchingstops at the stop layer 3 by virtue of the selectivity of the processwith respect to a titanium nitride layer. In this manner the futureportions of large thickness of the level of metallization of theintegrated circuit are defined.

FIG. 1 d shows that, subsequently, the mask 5 is removed.

Next, a second resin mask 8 is provided, see FIG. 1 e. This mask 8covers the regions previously covered by the first mask 5, which regionsare used to form the portions of large thickness, and it covers other,previously etched, regions which serve to form portions of smallthickness. Next, the integrated circuit is etched in aplasma-anisotropic process, so that the regions of the stop layer 3 andthe first metal layer 2 which are not protected by the mask 8 areremoved. As described hereinabove, the resin mask 8 is subsequentlyremoved.

As shown in FIG. 1 f, two types of patterns are obtained. A first typeis formed by the portions of large thickness 9, which are composed ofthe first metal layer 2, the stop layer 3 and the second metal layer 4,and a second type is formed by portions of small thickness 10 which arecomposed only of the first metal layer 2 and the stop layer 3, theplasma-etching process having stopped at the dielectric layer 1. Theportions of large thickness 9 may be used as inductors having athickness above 3 μm and a width of the order of 20 μm, while theportions of small thickness 10 constitute tracks of a logic circuit,their thickness and width ranging between 1 and 1.5 μm.

It is noted that the concave edges 7 of the portions of large thickness9 have not been modified by the plasma-etching step because they werecovered with the second resin mask 8, see FIG. le. As a result, theportions of large thickness 9 comprise an edge having a complex profile,i.e. the concave edge 7 at the level of the second metal layer 4 and astraight edge 11 at the level of the first metal layer 2. Thisarrangement does not present any drawback in terms of reduction of thesection of portion 9, because the surface of the region 6 where themetal of the layer 4 has been removed is very small with respect to thewhole of the portion of large thickness 9.

As a matter of fact, it is assumed that the width of the region 6 willbe smaller than or equal to the thickness of the second metal layer 4wherein it has been formed. The portion of large thickness 9 will havemaximally lost, at its top part, a part of its width which correspondsto approximately twice the thickness of the second metal layer 4. Theresistance value is not significantly increased thereby. An advantage ofa profile having two slopes is that it has an obtuse angle at the top ofthe step. By virtue of this characteristic, the concentration ofstresses in the upper passivating layer of the circuit is limited. Inshort, this method enables inductors having a very large thickness, offor example, 4 μm to be obtained, which cannot be manufactured in asingle metal layer since etching of such a layer would require thedeposition of a resin layer in a thickness equal to that of theinductor, which could not be insulated in a suitable manner.

In practice, this method can be used in combination with a first metallayer having a thickness ranging between 0.6 and 1 μm and a second metallayer having a thickness ranging between 1 and 4 μm.

The deposition of the three layers, i.e. first metal layer, stop layerand second metal layer, can be carried out one after the other, therebyachieving substantial savings in the production process.

The embodiment shown in FIGS. 2 a through 2 f is similar to thepreceding embodiment, with the exception that the first resin mask 5,which is shown for example in FIG. 2 c and which protects the secondmetal layer 4, is not removed but preserved for the following step shownin FIG. 2 d wherein the second resin mask 8 is deposited and,subsequently, developed in a second photolithographic step, whichresults in the circuit shown in FIG. 2 e.

This modification of the method enables the precision of the etchingprocess to be increased. As a matter of fact, the portion of largethickness 9 is defined only by the first mask 5, while the portions ofsmall thickness 10 are defined only by the second mask 8. In thismanner, any mistake in repositioning the photorepeater during thedevelopment of the second mask is avoided, which mistake could cause arelative displacement of the first metal layer 2 and the second metallayer 4 forming the portions of large thickness 9.

By virtue of the invention, an integrated circuit is obtained havingmetal portions of different thicknesses for the same level ofmetallization, which enables a better use of said level ofmetallization.

What is claimed is:
 1. An integrated circuit comprising at least onelevel of metallization, the level of metallization being provided withtracks and comprising metal portions of at least two differentthicknesses, characterized in that the level of metallization comprisesat the same time at least one inductor and at least one track, the trackbeing formed on a portion of small thickness, and the inductor beingformed on a portion of large thickness.
 2. A circuit as claimed in claim1, characterized in that the portion of large thickness comprises afirst part having a straight edge and a second part having a concaveedge.
 3. A circuit as claimed in claim 1, characterized in that thelevel of metallization comprises a first metal layer and a second metallayer, which are separated by a stop layer.
 4. A circuit as claimed inclaim 3, characterized in that the thickness of the second metal layeris larger than the thickness of the first metal layer.
 5. A method ofmanufacturing a level of metallization of an integrated circuit, thelevel of metallization being provided with tracks, comprising depositinga first metal layer, depositing a stop layer, depositing a second metallayer, depositing a first resin mask, then photoetching the second metallayer down to the stop layer, depositing a second resin mask, and thenphotoetching the stop layer and the first metal layer in such a mannerthat portions comprising the first metal layer and the second metallayer and portions comprising only the first metal layer remain intact.6. A method as claimed in claim 5, wherein the first mask is removedafter the second metal layer has been subjected to a photoetchingprocess.
 7. A method as claimed in claim 5, wherein the first mask ispreserved after the second metal layer has been subjected to aphotoetching process.